The integrated circuit (IC) industry is currently seeking ways to integrate logic circuits, such as a central processing unit (CPU) or microcontroller (MCU), and dynamic random access memory (DRAM) onto the same substrate. These CPU-DRAM integrated devices are being generally referred to as embedded DRAM microcontrollers. As is known in the art, current CPU/logic integrated circuit processes are optimized for circuit speed and metallic interconnect efficiency. These logic IC processes typically form current-leaky transistors. On the other hand, as is also known in the art, modern discrete DRAM IC processes used to manufacture state-of-the-art 16 Mbit and 64 Mbit DRAMs use a totally different process than a CPU logic process. Modern discrete DRAM processes are optimized for data retention whereby leakage current is reduced. DRAM processes result in the formation of very few metallic layers whereby speed and routing may be compromised to obtain better data retention. In essence, the transistors in a DRAM process are typically orders of magnitude less current leaky than the transistors of a logic/CPU process.
Due to these differences between a CPU logic process and a discrete DRAM process, integration of both logic and DRAM onto a single integrated circuit is not an easy task. It is clear that the combination of logic devices and DRAM memory devices on the same integrated circuit substrate must either compromise speed performance and signal routing capabilities in the CPU or compromise the data retention times of DRAM cells. It is believed that the latter may be the least problematic of the two choices. In this case, the CPU and DRAM are fabricated from the same logic IC process. When using this logic process, the data retention time for the embedded DRAM will be roughly two orders of magnitude less than the retention time of modern discrete DRAM devices (e.g., 16 Mbit and 64 Mbit devices now being shipped). By way of example, a discrete 16 Mbit or 64 Mbit DRAM that is currently manufactured using today's technology contains DRAM cells that have a data retention time of roughly tens of milliseconds. However, an embedded DRAM device manufactured using a logic process will typically have a data retention time of roughly 100 microseconds at maximum temperature, which is significantly reduced from the tens of milliseconds obtainable in discrete DRAM devices. This reduced data retention time is problematic as discussed below.
A DRAM relies upon capacitive charge for bit storage. This capacitive charge will adversely dissipate over a time known as the data retention time. To avoid loss of data due to dissipated charge, the capacitive charge of each DRAM cell must be refreshed within a specific time interval less than the data retention time. Due to the two order of magnitude reduction in data retention time for the embedded DRAM memory cells made by a logic/CPU process, refresh operations would need to be performed more frequently in embedded devices whereby operational bandwidth for functional read/write DRAM accesses will be reduced. In addition, the more frequent refresh cycles and faster dissipation of charge will most likely increase the power consumed by the embedded device.
The effect on DRAM access bandwidth, given the two orders of magnitude of reduction in DRAM retention for embedded devices, can be illustrated by numerical example. In this example, assume an embedded device with a 25 MHz clock, wherein the embedded DRAM uses a CAS-before-RAS (CBR) refresh technique which requires two clock periods per refresh operation in a burst mode. Also assume that refresh operations are controlled by clock edges generated from an on-chip DRAM refresh control circuit. Further assume, as is very common, that embedded DRAM arrays are smaller than discrete DRAM arrays whereby 128 embedded row addresses need to be generated to perform a complete array refresh whereas 2048 row addresses need to be generated to fully refresh a discrete DRAM device. Due to the two orders of magnitude difference between retention times, it is expected that DRAM cells in an embedded device need to be refreshed every 100 microseconds whereas discrete DRAM cells only need be refreshed every 20,000 microseconds. Given the above typical values, the time to refresh the entire embedded DRAM array is equal to two clock periods times the 40 nanosecond clock period times 128 memory rows which equals 10.24 microseconds. However, the time to refresh a discrete DRAM is equal to the two clock periods multiplied by a 40 nanosecond clock period multiplied by 2048 rows which equals 163.84 microseconds.
Using the above calculated times, the bandwidth consumed by refresh operations for the embedded DRAM device is 10.24 microseconds divided by the 100 microsecond refresh period which is roughly 10 percent. This means that 10% of the DRAM access bandwidth is consumed in an embedded device to keep the stored data fresh. The discrete DRAM bandwidth consumption is equal to 163 microseconds divided by the 20,000 microsecond refresh period which is roughly 0.8% bandwidth consumption. Therefore, an embedded DRAM device could consume 10 times more system access operational bandwidth than a discrete DRAM device. It should now be clear that timely performance and/or intelligently performing DRAM refreshes in embedded DRAMs becomes a serious concern whereas discrete DRAM devices are not concerned with improving refresh consumption of bandwidth since the bandwidth consumed in discrete DRAMs is insignificant.
In summary, embedded DRAM devices need to be refreshed more often than discrete DRAM devices whereby additional power is typically consumed and embedded DRAM device refresh operations typically consume a larger percentage of the operational bandwidth of the DRAM devices. Since a larger portion of the DRAM bandwidth is consumed, the embedded DRAM array is available for fewer read and write accesses whereby system performance may be degraded. Due to this result, system designers must attempt to perform refresh operations in a more intelligent manner whereby power can be conserved and more operational bandwidth can be returned to a logic circuit, that may include a CPU, integrated with an embedded DRAM array.
Discrete DRAM refresh operations, as are known in the art, are not intelligent refresh operations and do not need to be intelligent since the operational impairment and power consumption of refresh operations in a discrete DRAMs are generally not thought to be of big concern. In other words, since the bandwidth consumed by refresh operations in a discreet DRAM is less than 1% of the total bandwidth, there is little to be gained in complicating the design of a discrete DRAM device to perform intelligent refresh operations. However, intelligent refreshing of an embedded DRAM can significantly reduce the 10% DRAM refresh overhead bandwidth which justifies the added intelligent circuitry. The following paragraphs are a discussion of the common methods of refresh used in discrete DRAMs and these methods are shown herein to be inadequate to achieve the intelligent refreshing needed in embedded devices.
The discrete DRAMs may either perform a full sweep burst refresh, whereby all memory locations are refreshed sequentially in an uninterrupted manner in a single block of time, or perform distributed burst refreshes whereby sub-portions of the DRAM memory array are refreshed at different times that are spread out across an operational system access bandwidth of the DRAM. A refresh timer in a DRAM controller typically provides a time out signal which determines when a sweep burst or a distributed burst is to occur. The refresh operation will occur, in response to the time out signal, at those selected DRAM memory rows regardless of whether or not refresh is actually needed in these selected DRAM memory rows. Therefore, with unintelligent refresh operations in discrete DRAM, a row of memory that does not need refreshing (due to a previously performed write or read operation to this row) will be refreshed anyway thereby wasting some power and wasting operational DRAM bandwidth. In the discrete DRAMs, refreshes are performed with no intelligent processing of the access history or operational states of the memory rows. While the added power and reduced bandwidth is not a problem for discrete DRAMs as shown above, this added power and lost bandwidth would be severely degrading to the performance of an embedded DRAM device.
Discrete DRAM suppliers provide three standard methods for accomplishing non-intelligent refresh. One method is known as the row-address-strobe only (RAS-only) method, a second is referred to as the column-address-strobe (CAS) before row-address-strobe (RAS) method or CBR, and a third methodology is referred to as hidden refresh.
In the RAS-only scheme, a row address is provided by the DRAM controller where RAS is asserted but CAS remains deasserted. This operation results in all of the memory cells in the selected row being read out of the memory array and refreshed by a write-back operation which is built into the sense amplifiers of the DRAM device. The RAS-only refreshes are automatically performed through the DRAM array in an iterative and circular manner whereby a row is refreshed when scheduled, regardless of whether the charge in the row needs a refresh or not.
In the second scheme, the CBR scheme, the controller generates a CAS-before-RAS cycle and the DRAM utilizes an internal refresh row address generator to put the next refresh address onto the row address lines to the memory array. The row(s) associated with the row address is thereby refreshed within the DRAM array. This scheme uses the controller to generate control signals, but obviates the need for the DRAM controller to provide the row address and provides a method to refresh multiple rows in a memory comprised of multiple memory arrays. Both the RAS-only and the CAS before RAS (CBR) refresh methods are non-intelligent schemes which could waste power and consume significant bandwidth if these discrete DRAM methodologies were simply duplicated in an embedded DRAM environment without intelligent history control.
In the hidden refresh methodology, a CBR refresh cycle is appended to a system access where a system access is a read or write operation to a DRAM location. By keeping CAS low, providing a new row address internally, and toggling the RAS signal, a CBR refresh cycle is executed while the output data for a read is held. The refresh cycle time is not available to the user but the operation is hidden by the data being held valid at an output of the DRAM. Therefore, the "hidden" aspect of this technique refers to the data, and not the refresh time, where the refresh time is still lost to the system when using this technique. Therefore, if hidden refresh methodology is used in embedded DRAMs, it could also significantly consume bandwidth and cause considerable power consumption problems in microcontroller embedded DRAM designs as discussed above.
Therefore, a need exists in the industry for a more intelligent manner of scheduling refresh operations whereby: (1) greater system access bandwidth can be provided by an embedded DRAM device so that more performance can be achieved; and/or (2) less power is consumed by refresh operations internal to the embedded DRAM integrated circuit.